1. Field of the Invention
The present invention relates generally to semiconductor testing devices and to testing and/or burn-in methods for semiconductor devices, and particularly to the testing of high density integrated circuits such as DRAMs, SRAMs and embedded devices including "system on a chip" and graphic accelerators with embedded DRAM.
2. Description of the Related Art Integrated circuit devices, including DRAM and SRAM memory devices, are typically tested several times at the wafer level and again after dicing and packaging to ensure device quality and reliability. In a conventional testing process, individual devices on the wafer are tested to distinguish good devices from defective ones. The defects found at this stage of testing typically originated during device fabrication. If redundant circuits are present on the devices, a test/sort process is performed to detect reparable devices, which are typically laser repaired to activate the redundant circuitry. The good devices are sorted from the irreparable defective devices. A wafer separation unit, such as a scribe and break mechanism, separates the wafer into individual devices or die, and the good devices are individually packaged. After packaging, a pre-burn-in test (or open/short test) is typically performed to screen out packaging assembly defects, for example shorts or the existence of leakage current that will further degrade during burn-in. Burn-in is then performed in the form of a reliability stress test designed to accelerate failure mechanisms by operating at elevated temperatures. Following burn-in, a post burn-in test is performed to screen out the burn-in stress test defects. Those devices lost during burn-in are devices that likely would fail before the end of their specified life during normal operation. Defects are identified in these parts because the failure modes of the parts are accelerated by the burn-in process. The devices are then unloaded from the burn-in apparatus and a speed test at high temperature is performed. The packaged devices are then marked, and final tests are carried out to ensure that they will operate reliably at room temperature. Consequently, four or five different tests and anywhere from four to seventy-six hours of burn-in are required to ensure the quality and reliability of any given device.
High-density memory integrated circuits, e.g. 64 megabit or larger memory chips, require even longer test times than prior generation memories, since more time is needed to test these larger memory chips due to the longer execution test pattern. In addition, to achieve an acceptable level of yield from high density memories, extra die repair tests and processes are typically needed. At the end of these test and repair cycles, often 60-80% of the finally yielded good parts have undergone repairs. This more significant level of testing required by higher density memories can be costly and time-consuming. Conventional wafer probe technology may only test a single die at a time, or at most, up to 32 die simultaneously, and simultaneous testing of a greater number of die is constrained, in part, by the physical limitation of probe tip design.
Conventional wafer probing systems have relatively long probe tips which cause impedance mismatch problems when tests are carried out on the high density memory units. As the density of a device increases, high speed testing becomes necessary, and the tester must have good high frequency characteristics. Accordingly, probe lengths should be reduced as much as possible to allow testing at high speed or at high temperatures using a high frequency test signal. Due to the above limitations, post burn-in testing of high speed devices is typically performed after packaging. Such discrete component testing requires a large quantity of expensive burn-in systems, burn-in boards with expensive sockets that can accept packaged units, and additional labor associated with the loading and unloading of individual devices to and from the burn-in board. Further, these conventional processes typically scrap an additional one to three percent of the devices after post burn-in that would otherwise have been repairable through activation of redundant circuitry had they not been packaged before the burn-in test. The total cost per yielded packaged device is therefore unnecessarily increased by the equipment cost of the discrete component testing, the loss of devices that would be repairable had their defects been detected at the wafer level and the requirement of additional test cycles for the packaged parts. Accordingly, there is a need for a wafer level defect and reliability testing apparatus that can also perform many of the tests that currently take place after packaging. For example, it would be advantageous to perform the burn-in and high-temperature/high speed testing on all devices simultaneously while they are still in wafer form.